The three-stage Clos-network switch uses small switches as modules in each stage to build a switch with a large number of ports and therefore requires less hardware than that of a single-stage switch of the same size. Each of these modules can be a crossbar switch. Input-queued Clos-network (IQC) switches have queues in the input ports to store cells (variable-length packets are segmented into fixed-length packets, called cells, for internal switching) in case of input or output contention. The configuration of these switches is complex as output contention and path routing need to be resolved for every time slot before the transmission of packets occur. Although Clos-network switches reduce the hardware amount in terms of the number of crosspoints, the module size, and the number of modules required to implement high-capacity packet switches, there are other issues that can limit their scalability
Some of the issues that can limit the scalability of these switches are as follows. First, the time for configuring all modules before a packet is sent through the switch. This time requires a fast packet scheduler and an efficient exchange of scheduling information among the arbiters. Second, the number of ports (N), as a large N would require large-size hardware arbiters. For example, a switch with N=1024, using a scheduler with an implementation complexity of O(N2) and a time complexity of O(log N), would be difficult to build.
One strategy that simplifies the configuration complexity of Clos-network switches is the use of queues in the first- and third-stage modules. In this way, the scheduling of packets becomes a dispatching scheme issue. However, the queues in the first-stage modules need to work with a speedup of n+1 and those in the third-stage modules need to work with a speedup of m+1, where n is the number of input ports of the first-stage modules, and m is the number of second-stage modules. This makes it complex to build queued Clos-networks switches. Therefore, IQ Clos-network switches with bufferless switch modules seem to be a good alternative for large scale switches.
Considering that IQ Clos-network switches have no memory in any stage, except in the input ports, the switch modules are simple to design. An IQ Clos-network switch needs no memory speedup in the switch modules and is free of out-of-sequence forwarding that may occur in buffered Clos-network switches. As the input ports have virtual output queues (VOQs), where one queue per output port is allocated to store cells for that output, the IQ Clos-network switch avoids the head-of-line (HOL) blocking problem.
Various matching schemes to configure IQC switches have been proposed. Many of these schemes solve the configuration process in two phases: port matching first and routing thereafter, as routing uses the results of the port matching phase. The matching schemes based on port matching can be complex and time consuming. For instance, in a 1024×1024 switch these schemes require a scheduler able to simultaneously match 1024 input ports to 1024 output ports. However, a scheduler of that size may be complex to implement.